Static random access memory (SRAM) memory cells include a plurality of transistors. As technology advances, the sizes of the transistors may be reduced in order to reduce a size of the corresponding memory cell and associated memory array. Reducing the size of the transistors may result in increased variation in transistor operating characteristics and a corresponding decrease in operating margins, e.g., may result in read disturb.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.